To expedite the development of mask sets for fabricating integrated circuits (ICs), chip designers typically combine standard cells from cell libraries. These cell definitions are commonly referred to as “intellectual property,” (IP). Cells may contain geometrical objects such as polygons (boundaries), paths, and other cells. Objects in the cell are assigned to “layers” of the design. Typically, the cell definitions (IP) are provided by a cell library (or IP) vendor. The IP vendor develops each cell separately with the expectation that IC layouts designed using the cell will meet specifications. For example, the Taiwan Semiconductor Manufacturing Company, Ltd. of Taipei, Taiwan, provides a GDSII cell library of over 550 standard cells for 0.13 micron technology.
The IC designer selects the cells it wishes to use in an IC layout to provide whatever structures are required for a particular application. Each cell has one or more connectivity targets, which are predetermined points used to connect the patterns in a pair of cells. The configuration of cells (defined by the selection of GDS and a SPICE netlist) is submitted to a routing program, which connects the target-containing patterns of the adjacent cells to form complete sets of patterns for each mask layer.
When a design incorporates two cells adjacent to each other in an IC layout, the router identifies the location of the connectivity target in each cell, and constructs a connecting path between the targets, comprising one or more line segments. This connecting path is incorporated into the IC layout, so that the mask constructed from the connected cells includes continuous circuit paths.
Subsequently, the IC layout is submitted for verification (for example, using a program such as Calibre, by Mentor Graphics of Wilsonville, Oreg.). In verification, compliance with design rules is checked. For example, the line spacing between each pair of adjacent lines is compared to the relevant minimum for that line. If the line spacing is less than the minimum required for the width of the merged line, a design rule violation is identified.
To prevent misappropriation of their IP, many IP providers do not release IP GDS to their licensees, the IC designers. Instead, the IP providers only release their IP GDS and SPICE netlist to IC foundries, with whom the designers contract to fabricate the ICs. The designers are the foundries' direct customers. The designers need to have the IP GDS “merged” and verified before generating the tapeout data (where tapeout contains the design information that meets all of the complex process-specific design rules, has been fully verified and is ready to be used to generate masks). If the IP provider only releases its IP to the foundry, the customer must send its GDS and SPICE netlist to the foundry. In some cases, the foundry engineers execute the GDS merge, layout verification and tapeout. In other cases, the customers (e.g., the designer) may use a “customer room” at the foundry to do the merge operations themselves.
If the foundry engineers perform the IP merge, the foundry must allocate an engineer for the project. This may create human resource conflicts, because the foundry does not normally have dedicated engineering staff devoted to executing IP merge operations. If errors or violations are detected during the IP merge, the foundry's engineer sends the results to the customer for confirmation. The customer may then make changes to the design. This may require more than one iteration, and thus can cause delay in tapeout generation, especially if there is a time zone difference. If the foundry does not provide IP merge service on weekends and/or holidays, the delays may be even longer, regardless of the urgency of the project. Also, the foundry may charge the customer for its engineering services.
If the customer chooses to do the IP merge at the foundry's customer room, the customer must reserve the customer room. In some cases, the customer must wait because the customer room is not available. Depending on the locations of the foundry and the customer, the customer may have to incur travel expenses, and the person visiting the foundry to do the IP merge may lose time due to travel. The customer typically spends a great deal of time in the customer room during the IP merge operation. In some cases, the system processing time is large (e.g., hours), so that the customer may spend several days away from his or her normal job, doing nothing but the IP merge operation. Lastly, the foundry may charge the customer for the use of its room and/or computing resources.
An improved method and system for IP merge is desired.